Keynote Speakers

"Smart Microsystems Age Created by Heterogeneous Integration of Nano-Silicon Centric Technologies - My Personal View"
Dr.Nicky Lu

Dr.Nicky Lu

Chairman & CEO, Etron Technology

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As a researcher, design architect, entrepreneur and chief executive, Dr. Lu has dedicated his career to the worldwide IC design and semiconductor industry. He is Chairman, CEO and Founder of Etron Technology, Inc. and co-founded several other high-tech companies including Ardentec and Global Unichip Corp.
Dr. Lu worked for the IBM Research Division and then the Headquarters from 1982 to 1990 and won numerous IBM recognition awards, including an IBM Corporate Award. He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs. Dr. Lu designed a High Speed CMOS DRAM (HSDRAM) chip in 1984, 3X faster than normal DRAMs, the concept of which becomes core technologies of many major DRAMs. He was elected as an AdCom member of the IEEE Solid-State Circuits Society from 1977 to 1999, and is on the TPC (Technical Program Committees) of the IEEE International Solid States Circuits Conference (ISSCC) from 1988 to 2002 and of the Symposium on VLSI circuits since 1990, and as Chairman of A-SSCC (2014) and the TPC (2007). He is an IEEE Fellow, the recipient of the IEEE 1998 Solid-States Circuits Award, and a member of National Academy of Engineering of USA.
As a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan’s semiconductor industry in early 1990s, which later creates many Taiwan companies as prominent silicon chip suppliers, Dr. Lu was thus awarded the National Medal of Excellence in Science and Technology, Taiwan, R.O.C. Since 1999 he has pioneered DRAM Known-Good-Die Memory products enabling customers’ 3D stacked-die system chips. This work summoned the new rise of an IC Heterogeneous Integration Era as described in his plenary talk at the 2004 ISSCC, demonstrating a new 3D IC trend in parallel to the Moore’s Law.
Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 24 U.S. patents and has published more than 50 technical papers. He serves as Chairman of TSIA (Taiwan Semiconductor Industry Association) and WSC (World Semiconductor Council), and was Chairman of Global Semiconductor Alliance (GSA, the former FSA) from 2009 to 2011. He is an Outstanding Alumnus of National Taiwan University and a Chair Professor (2005-2007) and an Outstanding Alumnus of National Chiao Tung University.

Dr. Takeshi Abe

Professor, Department of Energy of Hydrocarbon Chemistry at Graduate School of Engineering, Kyoto University

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Dr. Abe received his BChE degree from Department of Industrial Chemistry, Faculty of Engineering, Kyoto University in 1992, and he has MS and PhD degrees from Graduate School of Engineering, Kyoto University. Upon completion of his PhD degree in 1996, he joined Graduate School of Engineering, Kyoto University as a Research Associate in 1997 and was promoted to Associate in 2002 and then to Professor in 2009.
Dr. Abe initially devoted to the graphite intercalation compounds and graphite negative electrode for lithium-ion batteries. His current research is based on lithium ion batteries and s-block metal batteries such as rechargeable magnesium batteries, focusing on interfacial phenomena. He has to his credit about over peer-reviewed 150 papers and several co-edited books about new technology for advance rechargeable batteries and electrochemistry.
His technical contributions have been recognized by awards of Sano Award for Young Scientists, Electrochemical Society of Japan in 2002, Battery Technology Award in 2006 from The Committee of Battery technology, The Electrochemical Society, Japan, Research Award, Carbon Society, Japan.

"Rapid Yield Improvement Using Intelligent Data Mining"
Vivek Jain

Mr. Vivek Jain

Senior Vice President, Technology and Manufacturing Group
Maxim Integrated

Abstract

Entitlement yield is the goal all manufacturing leaders strive to achieve; implementing improvement to get to entitlement yield quickly is critical for capturing the market before competitors, maximizing lifetime product revenue, driving low cost, and meeting customer quality requirements.
However, it is challenging to get to entitlement yield fast given the obstacles:
1. Multiple-month cycle time from start of wafer to getting yield information
2. Multiple yield issues (typical >3) to fix at any given time
3. Multiple iterations to fix a yield issue
4. Initial data looks promising, but high-volume data shows issues – multi factor issue
To be successful, it is important to use a methodology that provides a high-confidence/low-risk path to drive rapid yield improvement. Intelligent data mining is a versatile method that is applicable to new and ramping technologies, and it also addresses excursions in high-volume manufacturing. This method helps leaders understand sources of variation using existing information so that they can quickly figure out the key knobs to drive yield improvement and achieve entitlement yield.
In this paper, we will compare conventional yield improvement methodologies with intelligent data mining. These time-tested methodologies have been validated on deep sub-micron logic and memory as well as state-of-the-art analog and mixed-signal technologies.

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Vivek Jain is senior vice president of the Technology and Manufacturing Group for Maxim Integrated, Inc. The Technology and Manufacturing Group includes process development and all manufacturing operations.
Vivek joined Maxim in April 2007 as Vice President of Fab Operations and became Senior Vice President of Manufacturing Operations in 2009. Prior to joining Maxim, Vivek was a Plant Manager at Intel's Technology Development and Manufacturing facility in Santa Clara, CA. At Intel, he oversaw the process technology development and high-volume manufacturing of deep sub-micron logic and Flash memory technologies. Vivek has published more than 30 papers on process technology, semiconductor device reliability and performance. He holds over 10 patents in the field of semiconductor technology.
Vivek holds a BS degree in Chemical Engineering from the Indian Institute of Technology at New Delhi, an MS degree in Chemical Engineering from Penn State University, and an MS degree in Electrical Engineering from Stanford University. He is also a 2014 graduate of the Stanford Graduate School of Business Executive Program.

Masataka Osaki

Japan Country Manager, VP Corporate Sales, NVIDIA

Akira Minamikawa

Director, Semiconductor Value Chain; Technology Fellow, Omdia

Prof. Takayasu Sakurai

Prof. Takayasu Sakurai

Professor, School of Engineering, The University of Tokyo

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Takayasu Sakurai (IEEE S'77-M'78-SM'01-F'03) received the Ph.D. degree in EE from the University of Tokyo in 1981. In 1981 he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked extensively on interconnect delay and capacitance modeling known as Sakurai model and alpha power-law MOS model. From 1988 through 1990, he was a visiting researcher at the University of California Berkeley, where he conducted research in the field of VLSI CAD. From 1996, he has been a professor at the University of Tokyo, working on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC's and large-area electronics. He has published more than 600 technical publications including 100 invited presentations and several books and filed more than 200 patents. He is the executive committee chair for VLSI Symposia and a steering committee chair for the IEEE A-SSCC. He served as a conference chair for the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the A-SSCC, and VLSI symp., an executive committee member for ISLPED and a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is a recipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009 and 2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award, 2009 IEICE achievement award, 2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I patent of the year award and four product awards. He delivered keynote speech at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is also a domain research supervisor for nano-electronics area in Japan Science and Technology Agency. He is an IEICE Fellow and IEEE Fellow.